
TCK
(Input)
V IL
V IH
TDI
708
709
TMS
(Input)
TDO
(Output)
710
Input Data Valid
Output Data Valid
711
TDO
(Output)
Figure 31. Test Access Port Timing Diagram
TCK
(Input)
713
TRST
(Input)
712
Figure 32. TRST Timing Diagram
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 15
Freescale Semiconductor
39